The present invention relates to a metal oxide semiconductor (MOS) transistor and, more particularly, to a high voltage MOS transistor.
To establish an improved high voltage MOS transistor by preventing field concentration near the edge of a gate electrode, an attempt has been made in which there has been additionally provided a high resistant layer adjacent a drain as a part of the drain region, the conductivity type of the high resistant layer being the same as the drain.
The conventional transistor comprises a P type substrate, N.sup.+ type source layer, an N.sup.+ type drain layer, a P.sup.+ layer, an N.sup.- type high resistant layer, a source electrode, a drain electrode, insulating layers 8, 8' and 8", a gate electrode, field plate layers, and an additional field plate layer made of Al, polycrystalline silicon, or the like.
The P.sup.+ type layer surrounds the N.sup.+ type source layer for providing a gate channel for the transistor. The layer is formed by the diffusion-self-alignment process. A high voltage diffusion-self-alignment MOS transistor is described in Awane et al U.S. Pat. No. 4,058,822 issued Nov. 15, 1977, assigned to the present assignee, entitled "HIGH VOLTAGE, LOW ON-RESISTANCE DIFFUSION-SELF-ALIGNMENT METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF". The disclosure of this patent is incorporated herein by reference.
Around the N.sup.+ type drain layer, the N.sup.- type high resistant layer is provided for preventing field concentration in the edge of the N.sup.- type high resistant gate electrode. The layer constitutes a part of the drain region. Each of the source electrode and the drain electrode is composed of Al, polycrystalline silicon, or the like. Each of the field plate layers extends from each of the source electrode and the drain electrode. The gate electrode is made of Al or polycrystalline silicon, called a silicon gate. The field plate layer is prepared simultaneously with the preparation of the silicon gate.
The field plate layer functions to reduce field concentration in the edges of the gate electrode and in the boundary between the N.sup.+ type layer and the N.sup.- type layer.
If one of the field plate layers extends over an acceptable limitation, a reverse field plate effect may be generated which is applied to the drain portion by the layer or to the edge of the gate electrode by the layer. This reduces the value of a sustained voltage.
To eliminate the generation of the reverse field plate effect, the above-mentioned structure of the transistor includes a region A of the N.sup.- type high resistant layer not covered by the field plate layers, made of Al or the polycrystalline silicon. Undesirably, the amount of a sustainable voltage in the ON condition, the amount of the drain current and the value of R.sub.ON will inevitably vary according to this structure.